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A Bit-Operation Algorithm of the Median-Cut Quantization and Hardwere Architecture
http://hdl.handle.net/10191/6544
http://hdl.handle.net/10191/6544f32f2d28-0766-4f5f-b239-0030ceefb187
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
e83-a_2_320.pdf (1.2 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2008-08-01 | |||||
| タイトル | ||||||
| タイトル | A Bit-Operation Algorithm of the Median-Cut Quantization and Hardwere Architecture | |||||
| タイトル | ||||||
| タイトル | A Bit-Operation Algorithm of the Median-Cut Quantization and Hardwere Architecture | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | adaptive quantization | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | median value | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | motion estimation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | VLSI | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 著者 |
Muramatsu, Shogo
× Muramatsu, Shogo× Kiya, Hitoshi× Yamada, Akihiko |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 6118 | |||||
| 姓名 | 村松, 正吾 | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | In this paper, an algorithm of the median-cut quantization (MCQ) is proposed. MCQ is the technique that reduces multi-valued samples to binary-valued ones by adaptively taking the median value as the threshold. In this work, the search process of the median value is derived from the quick-sort algorithm. The proposed algorithm searches the median value bit by bit, and samples are quantized during the search process. Firstly, the bit-serial procedure is shown, and then it is modified to the bit-parallel procedure. The extension to the multi-level quantization is also discussed. Since the proposed algorithm is based on bit operations, it is suitable for hardware implementation. Thus, its hardware architecture is also proposed. To verify the significance, for the application to the motion estimation, the performance is estimated from the synthesis result of the VHDL model. | |||||
| 書誌情報 |
IEICE transactions on fundamentals of electronics, communications and computer sciences en : IEICE transactions on fundamentals of electronics, communications and computer sciences 巻 E83-A, 号 2, p. 320-328, 発行日 2000-02 |
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| 出版者 | ||||||
| 出版者 | The Institute of Electronics, Information and Communication Engineers | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 09168508 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10826239 | |||||
| 権利 | ||||||
| 権利情報 | copyright©2000 IEICE | |||||
| 著者版フラグ | ||||||
| 値 | publisher | |||||
| 異版である | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | URI | |||||
| 関連識別子 | http://www.ieice.org/jpn/trans_online/ | |||||
