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Lifting Architecture of Invertible Deinterlacing
http://hdl.handle.net/10191/6500
http://hdl.handle.net/10191/65007ff671b8-73f2-4467-8b92-51c935197e0a
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
e86-a_4_779.pdf (1.2 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2008-07-25 | |||||
| タイトル | ||||||
| タイトル | Lifting Architecture of Invertible Deinterlacing | |||||
| タイトル | ||||||
| タイトル | Lifting Architecture of Invertible Deinterlacing | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | deinterlacing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | discrete wavelet transforms | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | lifting scheme | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | JPEG2000 | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | intra-frame-based motion picture coding | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 著者 |
Soyama, Tatsuumi
× Soyama, Tatsuumi× Ishida, Takuma× Muramatsu, Shogo× Kikuchi, Hisakazu× Kuge, Tetsuro |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 6029 | |||||
| 姓名 | 村松, 正吾 | |||||
| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 6030 | |||||
| 姓名 | 菊池, 久和 | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase. | |||||
| 書誌情報 |
IEICE transactions on fundamentals of electronics, communications and computer sciences en : IEICE transactions on fundamentals of electronics, communications and computer sciences 巻 E86-A, 号 4, p. 779-786, 発行日 2003-04 |
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| 出版者 | ||||||
| 出版者 | The Institute of Electronics, Information and Communication Engineers | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 09168508 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10826239 | |||||
| 権利 | ||||||
| 権利情報 | copyright©2003 IEICE | |||||
| 著者版フラグ | ||||||
| 値 | publisher | |||||
| 異版である | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | URI | |||||
| 関連識別子 | http://www.ieice.org/jpn/trans_online/ | |||||
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Cite as
Soyama, Tatsuumi, Ishida, Takuma, Muramatsu, Shogo, Kikuchi, Hisakazu, Kuge, Tetsuro, 2003, Lifting Architecture of Invertible Deinterlacing: The Institute of Electronics, Information and Communication Engineers, 779–786 p.
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