@article{oai:niigata-u.repo.nii.ac.jp:00001879, author = {Soyama, Tatsuumi and Ishida, Takuma and Muramatsu, Shogo and Kikuchi, Hisakazu and Kuge, Tetsuro}, issue = {4}, journal = {IEICE transactions on fundamentals of electronics, communications and computer sciences, IEICE transactions on fundamentals of electronics, communications and computer sciences}, month = {Apr}, note = {Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.}, pages = {779--786}, title = {Lifting Architecture of Invertible Deinterlacing}, volume = {E86-A}, year = {2003} }