{"_buckets": {"deposit": "75886c3b-ec3b-4fd2-a206-dba5ddaa3f69"}, "_deposit": {"id": "1887", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "1887"}, "status": "published"}, "_oai": {"id": "oai:niigata-u.repo.nii.ac.jp:00001887", "sets": ["454", "425"]}, "item_5_biblio_info_6": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2001-08", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "8", "bibliographicPageEnd": "1959", "bibliographicPageStart": "1951", "bibliographicVolumeNumber": "E84-A", "bibliographic_titles": [{"bibliographic_title": "IEICE transactions on fundamentals of electronics, communications and computer sciences"}, {"bibliographic_title": "IEICE transactions on fundamentals of electronics, communications and computer sciences", "bibliographic_titleLang": "en"}]}]}, "item_5_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "A unified polyphase representation of analysis and synthesis filter banks is introduced in this paper, and then the efficient implementation on digital signal processors (DSP) is investigated. Especially, the number of memory accesses, power consumption, processing accuracy and the required instruction cycles are discussed. Firstly, a unified representation is given, and then two types of procedures, SIMO system-based and MISO system-based procedures, are shown, where SIMO and MISO are abbreviations for single-input/multiple-output and multiple-input/single-output, respectively. These procedures are compared to each other. It is shown that the number of data load in SIMO system-based procedure is a half of that in MISO system-based procedure for two-channel filter banks. The implementation of M-channel filter banks is also discussed.", "subitem_description_type": "Abstract"}]}, "item_5_full_name_3": {"attribute_name": "著者別名", "attribute_value_mlt": [{"nameIdentifiers": [{"nameIdentifier": "6076", "nameIdentifierScheme": "WEKO"}], "names": [{"name": "村松, 正吾"}]}, {"nameIdentifiers": [{"nameIdentifier": "6077", "nameIdentifierScheme": "WEKO"}], "names": [{"name": "菊池, 久和"}]}]}, "item_5_publisher_7": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "The Institute of Electronics, Information and Communication Engineers"}]}, "item_5_relation_31": {"attribute_name": "異版である", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "http://www.ieice.org/jpn/trans_online/", "subitem_relation_type_select": "URI"}}]}, "item_5_rights_15": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "copyright©2001 IEICE"}]}, "item_5_select_19": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_select_item": "publisher"}]}, "item_5_source_id_11": {"attribute_name": "書誌レコードID", "attribute_value_mlt": [{"subitem_source_identifier": "AA10826239", "subitem_source_identifier_type": "NCID"}]}, "item_5_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "09168508", "subitem_source_identifier_type": "ISSN"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Mizutani, Naoki"}], "nameIdentifiers": [{"nameIdentifier": "6073", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Muramatsu, Shogo"}], "nameIdentifiers": [{"nameIdentifier": "6074", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Kikuchi, Hisakazu"}], "nameIdentifiers": [{"nameIdentifier": "6075", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2019-07-29"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "e84-a_8_1951.pdf", "filesize": [{"value": "1.2 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 1200000.0, "url": {"label": "e84-a_8_1951.pdf", "url": "https://niigata-u.repo.nii.ac.jp/record/1887/files/e84-a_8_1951.pdf"}, "version_id": "348d71bd-9578-4523-bec5-6563b10503a3"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "digital signal processor (DSP)", "subitem_subject_scheme": "Other"}, {"subitem_subject": "filter bank", "subitem_subject_scheme": "Other"}, {"subitem_subject": "wavelet transform", "subitem_subject_scheme": "Other"}, {"subitem_subject": "multiplier and accumulator (MAC)", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures"}, {"subitem_title": "Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures", "subitem_title_language": "en"}]}, "item_type_id": "5", "owner": "1", "path": ["454", "425"], "permalink_uri": "http://hdl.handle.net/10191/6497", "pubdate": {"attribute_name": "公開日", "attribute_value": "2008-07-17"}, "publish_date": "2008-07-17", "publish_status": "0", "recid": "1887", "relation": {}, "relation_version_is_last": true, "title": ["Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures"], "weko_shared_id": null}