2024-03-28T11:36:11Z
https://niigata-u.repo.nii.ac.jp/oai
oai:niigata-u.repo.nii.ac.jp:00001904
2022-12-15T03:34:45Z
423:424:425
453:454
FFT-Based Implementation of Sampling Rate Conversion with a Small Number of Delays
FFT-Based Implementation of Sampling Rate Conversion with a Small Number of Delays
Zou, Xiaoxia
Muramatsu, Shogo
Kiya, Hitoshi
copyright©1997 IEICE
multirate signal processing
sampling rate conversion
overlap-add/save method
Block delay caused by using fast Fourier transform (FFT), and computational complexity in sampling rate conversion system are considered in this paper. The relationship between the number of block delays and the computational complexity is investigated. The proposed method can avoid the redundant operations of sampling rate conversion completely and moreover provide a good trade-off between the number of block delays and the computational complexity. As a result, ti is shown that with the proposed method, the sampling rate conversion can be realized more efficiently under a small number of block delays.
The Institute of Electronics, Information and Communication Engineers
1997-08
eng
journal article
http://hdl.handle.net/10191/6540
https://niigata-u.repo.nii.ac.jp/records/1904
http://www.ieice.org/jpn/trans_online/
AA10826239
09168508
IEICE transactions on fundamentals of electronics, communications and computer sciences
IEICE transactions on fundamentals of electronics, communications and computer sciences
E80-A
8
1367
1375
https://niigata-u.repo.nii.ac.jp/record/1904/files/e80-a_8_1367.pdf
application/pdf
607.9 kB
2019-07-29